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eZ80Acclaim! Flash Microcontrollers
EZ80F91 Product Brief
PB010704-0103
Product Block Diagram
EZ80F91 MCU 256KB+ 8KB SRAM 512B Flash 32-Bit GPIO
10/100Mbps Ethernet MAC 8KB Frame Buffer Infrared Encoder/ 2 UART Decoder 4 PRT 4 CS +WSG WDT JTAG ZDI I2C SPI Real-Time Clock PLL
* Four Counter/Timers with prescalers supporting event counting, input capture, output compare, and PWM modes * Watch-Dog Timer with internal RC clocking option * Real-time clock with on-chip 32kHz oscillator, selectable 50/60 Hz input, and separate RTC_VDD pin for battery backup. * Glueless external memory interface with 4 Chip-Selects/Wait-State Generators and external WAIT input pin. Supports Intel and Motorola buses. * JTAG Interface supporting emulation features * Low-power PLL and on-chip oscillator * Programmable-priority vectored interrupts, nonmaskable interrupts, and interrupt controller * New DMA-like eZ80(R) CPU instructions * Power management features supporting HALT/ SLEEP modes and selective peripheral powerdown controls * 144-pin LQFP package * 3.0-3.6 V supply voltage with 5 V tolerant inputs * Operating Temperature Ranges: - Standard: 0C to +70C - High: 0C to +105C
Features
The EZ80F91 microcontroller is a member of ZiLOG's eZ80Acclaim! product family, which offers on-chip Flash versions of ZiLOG's eZ80 (R) processor core. The EZ80F91 offers the following features: * 50MHz High-Performance eZ80(R) CPU * 256KB Flash Program Memory plus extra 512B device configuration Flash memory * 8KB on-chip high-speed SRAM * 32 bits of General-Purpose I/O * 10/100BaseT Ethernet Media Access Controller (EMAC) with 8KB High-Speed Frame Buffer * IrDATM-compatible Infrared Encoder/Decoder * 2 UARTs with independent baud rate generators * I2C with independent clock rate generator * SPI with independent clock rate generator
General Description
The EZ80F91 device is an industry first, featuring a high-performance 8-bit microcontroller with an integrated 10/100 BaseT Ethernet Media Access controller (EMAC). It is a power-efficient, optimized pipeline architecture microcontroller with a maximum operating speed of 50 MHz. Offering on-chip Flash memory, SRAM, Ethernet MAC, and rich peripherals, the EZ80F91 is well-suited for industrial, communication, automation, security, and embedded Internet applications.
ZiLOG Worldwide Headquarters * 532 Race Street * San Jose, CA 95126 Telephone: 408.558.8500 * Fax: 408.558.8300 * www.ZiLOG.com
EZ80F91 Product Brief
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eZ80(R) CPU Core
The CPU can operate in Z80-compatible (64 KB) mode or full 24-bit (16 MB) addressing mode. Considering both the increased clock speed and processor efficiency, the eZ80 (R)'s processing power rivals the performance of 16-bit microprocessors. The eZ80(R) improves on the world-famous Z80 architecture. Like the Z80, it features dual bank registers for fast context switching. eZ80 (R)
EZ80F91 Peripherals Description
On-Chip Memory
pendent Interface (MII) for simple connection to an external Physical Layer interface (PHY) device. The EZ80F91 delivers high performance and overall cost effectiveness as an embedded network microcontroller. High performance is achieved by optimizing the internal bus design of the eZ80(R) CPU with shared memories, dedicated Ethernet Tx/Rx DMAs, and Tx/Rx FIFOs. This bus design provides the highest data throughput over the Ethernet interface, yet requires minimum eZ80 (R) CPU intervention and minimizes system loading.
Infrared Encoder/Decoder
The EZ80F91 device offers 256 KB of Flash program memory. A separate page of 512 bytes Flash memory is available for general device configuration data. * Single power supply operation * Page erase feature: 1024 bytes/page * Fast page erase and byte program operation * 60 ns maximum access time * Endurance: 20,000 write cycles (typical) * Data retention: greater than 100 years @ room temperature In addition, 8 KB of high-speed, relocatable SRAM is available for general application use.
General-Purpose Input/Output
* * * *
Supports IrDA SIR format Operates seamlessly with on-chip UART Interfaces with IrDA-compliant transceivers Supports transmit/receive to 115Kbps
Universal Asynchronous Receiver/Transmitter
There are 32 bits of General-Purpose Input or Output (GPIO). All GPIO pins are individually programmable and support the following I/O modes: input, output, open drain, open source, level-triggered interrupts (High or Low), edge-triggered interrupts (High or Low), dual edge-triggered interrupts, and alternate function. Eight of the output pins can drive 10 mA each (Port A), while 16 other pins feature Schmitt-trigger input buffers (Ports B and C).
10/100BaseT Ethernet MAC
Each of the two Universal Asynchronous Receiver/ Transmitter (UART) channels contains a transmitter, a receiver, control logic/registers, and a Baud Rate Generator (BRG). * The Baud Rate Generator produces a lower-frequency bit clock from the system clock. All standard baud rates up to 115Kbps (and higher) are supported. * The UART module implements all of the logic required to support asynchronous communications, hardware flow control, and 9-bit character format. The module also contains separate 16byte-deep transmit and receive FIFOs.
Inter-Integrated Circuit
The EZ80F91 device features an integrated IEEE 802.3 Ethernet controller with a total of 8 KB of dynamically-configurable Tx/Rx frame buffer. It supports speeds of 10 and 100 Mbps, full duplex operation, and an industry-standard Media Inde-
The Inter-Integrated Circuit (I2C) channel contains control registers and its own clock rate generator. The I2C interface operates in four modes: Master Transmit or Receive, and Slave Transmit or Receive. A standard and fast I2C speed of 100kbps and 400kbps are supported.
Serial Peripheral Interface
The Serial Peripheral Interface (SPI) channel contains control registers and its own clock rate generator. The SPI is a synchronous serial interface
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eZ80Acclaim! Flash Microcontrollers
EZ80F91 Product Brief
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allowing multiple SPI devices to be interconnected. The SPI interface may be configured to operate as a master or a slave.
Programmable Reload Timers
The EZ80F91 provides four independent Programmable Reloadable Counter Timers (PRT) to handle complex timing functions. Each timer is a 16-bit downcounter and offers a 4-bit clock prescaler with four selectable taps for CLK / 4, CLK / 16, CLK/64 and CLK/256. The timers can operate in basic mode supporting SINGLE-PASS or CONTINUOUS count. Additional features include 4 input captures, 4 output compares, 2 external event counters, and 4 PWMs that can operate independently or in unison. Any one of the input capture pins can be programmed as master PWM powertrip inputs.
Watch-Dog Timer
individually programmed on a 64KB boundary. I/ O chip selects can choose a 256-byte section of I/O space. The WAIT input pin allows interface with slow peripherals. Z80, Intel, and Motorola bus modes are supported.
JTAG Interface
An IEEE 1149.1-compatible five-pin test access port (TAP) is provided to interface with on-chip test logic defined by that standard. This TAP also includes Boundary Scan functions. For IEEE 1149.1 compliance, a pull-up resistor is required on pin TDI. Additionally, the TAP is used to control the on-chip emulation/debugging capabilities. Some included features are: software break points, a 64-word trace buffer, complex break points using address and data masks, and cascadable triggers.
PLL and On-Chip Crystal Oscillator
The Watch-Dog Timer (WDT) features four programmable time-out periods: 218, 222, 225, or 227 system clock cycles. It can operate from either the main system clock, the on-chip 32 kHz oscillator (from the RTC), or the internal RC oscillator. The time-out action of the WDT is user-programmable for either a hardware reset or a nonmaskable interrupt to the eZ80(R) CPU. The source of action taken after a WDT time-out is indicated by a WDT status bit.
Real-Time Clock
The EZ80F91 features a complete, low-power, programmable PLL that can be selected to generate the system clock. Taking its input from the on-chip crystal oscillator, the PLL can generate system clock speeds up to 50MHz from low-cost, low-frequency external crystals in the range of 1-10MHz..
ZiLOG Debug Interface
The ZiLOG Debug Interface (ZDI) incorporates most of the functions of an In-Circuit Emulator onchip. ZDI allows the user to single-step code, change registers, edit programs, and view status of internal registers.
Block Transfer Instructions
The real-time clock (RTC) allows counting of seconds, minutes, hours, days-of-the-week, day-ofthe-month, month, year, and century. Alarms and interrupts can be set for seconds, minutes, hours, and day-of-the-week. The real-time clock input can be taken from the on-chip 32kHz oscillator or from a 50/60 Hz input. The real-time clock operates from an isolated RTC_VDD pin to allow constant operation from a battery.
Chip-Select/Wait State Generator and WAIT Pin
Block transfer instructions with expanded repeat capability have been added to the eZ80 (R) CPU. They provide high-performance data transfer similar to hardware DMAs.
Power Management
Several power management features are supported on the EZ80F91. Two peripheral power-down registers allow independent clock gating of on-chip peripherals under software control while operating under normal conditions. The eZ80 (R) CPU can write to these control registers to disable the clock
Four independent chip selects are available to facilitate glueless interface to system memory and external devices. Each chip select can be configured for up to 7 wait states, and supports either memory or I/O space. Memory chip selects can be
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eZ80Acclaim! Flash Microcontrollers
EZ80F91 Product Brief
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from driving any one of the peripherals when they are inactive. In addition, execution of the HALT instruction suspends eZ80(R) CPU operation and eliminates clock power associated with the eZ80(R) CPU core. Normal operation can be restored via external and peripheral interrupts or hardware reset. Execution of a sleep (SLP) instruction provides the lowest power consumption. In SLEEP mode, only the on-chip RTC 32kHz crystal oscillator remains active to drive the RTC and the WDT. All other peripherals, the system clock, and the primary oscillator are disabled. An RTC alarm, a WDT time-out, or hardware reset can reset the device.
* High temperature: 0C to +105C * Supply current @ 50MHz: 50mA (typical) * Supply current in HALT mode with peripherals powered down: <5mA (typical) * Supply current in SLEEP mode: <50A (typical)
Support Tools
The following development tools are available to program and debug the EZ80F91 device: * Development board with eZ80(R) CPU plug-in module * IPWorksTM TCP/IP software stack * Operating System * ANSI C-Compiler * ZiLOG Developer's Studio Integrated Development Environment (ZDS IDE) including assembler, linker, debugger, and simulator
Electrical Features Summary
* Power supply: 3.3V 0.3V * Standard temperature: 0C to 70C
Related Products
Other integrated devices of interest are:
eZ80190 50 MHz eZ80(R) CPU, 8KB SRAM, 16x16 Multiply with 40-bit Accumulators, 32 bits GPIO, 6 Counter Timers with Prescalers, WDT, 4 channel CS+WSG, 2-Channel DMA, 2 UZI Channels, ZDI, On-Chip Oscillator. 20MHz and 50MHz eZ80(R) CPU, low-power modes, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4-channel CS, JTAG, ZDI. 20MHz eZ80(R) CPU, low-power modes, 128KB+256B Flash, 8KB SRAM, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4 channel CS+WSG, JTAG, ZDI, PLL. 20MHz eZ80(R) CPU, low-power modes, 64KB+256B Flash, 4KB SRAM, 24 bits GPIO, IrDA, 2 UART, I2C, SPI, 6 Counter Timers with I/O features, WDT, RTC, 4 channel CS+WSG, JTAG, ZDI.
eZ80L92 eZ80F92
eZ80F93
Z80S180TM Improved Z80 CPU, 1MB MMU, 2 DMA, 2 16-bit PRTs, 2 UARTs, CSIO, up to 33MHz clock speed Z80181 Z80182 Z84C00 Z84C15 Z8S180 CPU, SCC, CTC, 16-bit GPIO, up to 33MHz clock speed Z8S180 CPU, 2 ESCC, 24-bit GPIO, 16550 Mimic interface, up to 33MHz clock speed Z80TM CPU (up to 20MHz) Z80TM CPU, 2 SIO, 4x8 CTC, 2 PIO, WDT, up to 16 MHz clock speed
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eZ80Acclaim! Flash Microcontrollers
EZ80F91 Product Brief
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Block Diagram
Ethernet MAC Signals (18)
Ethernet MAC RTC_XOUT RTC_XIN RTC_VDD
Battery backup
8K Byte FIFO (SRAM)
Real-Time Clock BUSACK Bus Controller & Arbiter DATA[7:0] BUSREQ IORQ MREQ INSTRD RD WR 256KB Program Flash + 512Bytes Config Flash
SCL SDA
I2C Serial Interface
SCK SS MISO MOSI
SPI Serial Parallel Interface ADDR[23:0]
HALT_SLP eZ80 CPU WAIT NMI RESET JTAG Debug Interface JTAG Signals (6)
CTS0/1 DCD0/1 DSR0/1 DTR0/1 RI0/1 RTS0/1 RXD0/1 TXD0/1 UART Universal Asynchronous Receiver/ Transmitter (2)
Interrupt Vector [7:0] Interrupt Controller
Chip Select & Wait State Generator
CS0 CS1 CS2 CS3 DATA[7:0] ADDR[23:0]
IrDA Encoder/ Decoder
GPIO General Purpose I/O Port (4x 8-bit)
Crystal Oscillator, PLL and System Clock Generator
Programmable Reload Timer/Counter (4)
WDT Watchdog Timer Internal RC Osc
OC0/1/2/3 PWM0/1/2/3
LOOP_FILT
XOUT
IR_RXD
IR_TXD
Figure 1. EZ80F91 Block Diagram
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IC0/1/2/3
PA[7:0]
PB[7:0]
PC[7:0]
PD[7:0]
EC0/1
XIN
PHI
eZ80Acclaim! Flash Microcontrollers
EZ80F91 Product Brief
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Pin Diagram
VSS VDD TX_ER TX_CLK 130 TX_EN TXD0 TXD1 TXD2 TXD3 COL CRS VSS VDD PA7/PWM3 120 PA6/PWM2/EC1 PA5/PWM1/TOUT1 PA4/PWM0/TOUT0 PA3/PWM3/OC3 PA2/PWM2/OC2 PA1/PWM1/OC1 PA0/PWM0/OC0 VSS VDD PHI 110 SCL SDA
144 WP MDIO MDC RXD3 140 RXD2 RXD1 RXD0 RX_DV RX_CLK RX_ER
40
50
60
Ordering Information
Part EZ80F91AZ050SC EZ80F91AZ050HC EZ80F910200ZCO PSI 50MHz, Standard Temperature 50MHz, High Temperature Description EZ80F91 device EZ80F91 device
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VDD VSS D0 D1 D2 D3 D4 D5 D6 D7 VDD VSS IORQ MREQ RD WR INSTRD WAIT RESET NMI BUSREQ BUSACK VDD VSS RTC_XIN RTC_XOUT RTC_VDD VSS HALT_SLP TMS TCK TRIGOUT TDI TDO TRST VSS
Figure 2. EZ80F91 144-Pin LQFP Pin Configuration
Development Kit, standard version Complete eZ80Acclaim! Development Kit
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A0 A1 A2 A3 A4 VDD VSS A5 A6 A7 A8 A9 A10 VDD VSS A11 A12 A13 A14 A15 A16 VDD VSS A17 A18 A19 A20 A21 A22 A23 VDD VSS CS0 CS1 CS2 CS3
1
10
144-Pin LQFP
20
30
36
108 VSS PB7/MOSI PB6/MISO PB5/IC3 PB4/IC2 PB3/SCK PB2/SS PB1/IC1 100 PB0/IC0/EC0 VSS VDD PC7/RI1 PC6/DCD1 PC5/DSR1 PC4/DTR1 PC3/CTS1 PC2/RTS1 PC1/RxD1 90 PC0/TxD1 VSS VDD PLL_VDD XOUT XIN PLL_VSS LOOP_FILT VSS VDD 80 PD7/RI0 PD6/DCD0 PD5/DSR0 PD4/DTR0 PD3/CTS0 PD2/RTS0 PD1/RxD0/IR_RXD 73 PD0/TxD0/IR_TXD
EZ80F91 Product Brief
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This publication is subject to replacement by a later edition. To determine whether a later edition exists, or to request copies of publications, contact: ZiLOG Worldwide Headquarters
532 Race Street San Jose, CA 95126 USA Telephone: 408.558.8500 Fax: 408.558.8300 www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or service names mentioned herein may be trademarks of the companies with which they are associated. (c)2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no warranty of merchantability or fitness for any purpose Except with the express written approval of ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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eZ80Acclaim! Flash Microcontrollers

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